New Linux & RISC-V: PINE64 Puts Hardware on Hold, StarFive Goes Server-Class, and Linux 7.2 Arrives

The small-computing world usually moves forward through new boards, faster processors, and increasingly ambitious hardware.

This week is a little different.

PINE64 says it currently has no plans to manufacture more of its Linux devices as high DRAM and eMMC prices continue to squeeze production. At the same time, StarFive is pushing RISC-V in the opposite direction, introducing a server-class CPU core aimed far beyond the SBC market.

And underneath both of those stories, Linux 7.2 has officially arrived with another round of improvements for RISC-V, Arm boards, and newer PC hardware.

Together, the three developments give us an interesting snapshot of where open hardware and Linux computing are heading.

PINE64 has spent more than a decade building some of the more unusual devices in the open-hardware world.

The original Pine A64 helped establish the company in the SBC market back in 2015, and the lineup eventually grew to include RISC-V boards, Linux smartphones, tablets, laptops, and the PineNote e-ink tablet.

For now, though, much of that Linux hardware lineup is effectively on hold.

PINE64 recently posted an update on its Telegram and Mastodon channels reminding the community that, because of the ongoing DRAM and eMMC shortage, there are currently no plans to continue producing additional Linux devices in the near future.

More importantly, the company says any decision to restart production will depend on memory pricing after the middle of 2027.

The problem itself isn't new.

PINE64 first flagged the issue back in March following discussions at FOSDEM 2026, confirming that production of the PineTab2, PineNote, and PinePhone had already been suspended because of the memory shortage.

At the time, PineStore founder TL Lim said he didn't want to significantly raise hardware prices to compensate, so production was halted while remaining inventory continued to sell.

The latest update gives us a much clearer idea of how long that situation could last.

PINE64 estimates that remaining PineNote and PineTab2 inventory could run out within roughly three months. Once that stock disappears, customers shouldn't assume another batch will quickly follow.

Not everything PINE64 makes is affected.

Products including the PineTime, PineVoice, and Pinecil will continue production as usual. These devices are built around microcontrollers and don't depend on the same combination of external DRAM and eMMC storage that's creating problems for the Linux lineup.

Development of the upcoming PineTime Pro is also continuing, with demo firmware already running basic drivers for the display, touchscreen, motion sensor, GPS, buttons, heart-rate sensor, battery charger, motor, microphone, and speaker.

That split is telling.

A device like the Pinecil can be built around relatively straightforward microcontroller hardware. A full Linux SBC, tablet, or smartphone needs considerably more memory and storage, and those components make up a meaningful part of the bill of materials.

For a company like PINE64, simply passing dramatically higher component prices on to customers isn't necessarily an attractive option.

PINE64 has historically sold much of its community hardware on relatively thin margins. Keeping an enthusiast Linux tablet or SBC affordable is part of what makes the hardware interesting in the first place.

Raise the price too much, and suddenly it starts competing with faster, more polished mainstream hardware.

So instead, PINE64 is waiting.

That's unfortunate for anyone hoping to see another wave of PinePhone, PineTab, PineNote, or Linux SBC hardware in the immediate future, but it also highlights a larger problem facing the maker market.

Low-cost memory has helped make inexpensive Linux computers possible. When DRAM and flash prices rise sharply, smaller manufacturers have far less room to absorb those increases than companies shipping millions of mainstream PCs and phones.

PINE64 may be one of the more visible examples, but it probably won't be the only hardware company feeling that pressure.

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While PINE64 is being forced to slow down, StarFive is pushing RISC-V considerably further up the performance ladder.

On August 19, StarFive officially introduced the Dubhe-100, a new 64-bit RISC-V CPU core designed for servers, high-performance computing, and other demanding workloads.

That's a big shift from the StarFive most makers are familiar with.

The company became widely known through chips such as the JH7100 and JH7110, which powered early RISC-V Linux boards including the VisionFive and VisionFive 2.

Dubhe-100 isn't another SBC processor.

It's commercial CPU IP intended to become the foundation of much larger server-class chips.

The core is compliant with the newer RVA23 application profile and implements an RV64GCBVH instruction set with RISC-V Vector and Vector Crypto support.

Architecturally, it's far beyond the relatively modest cores found in most affordable RISC-V development boards.

Dubhe-100 uses a 15-stage pipeline, six-wide issue, and deep out-of-order execution backed by a 512-entry reorder buffer. It also includes multicore cache coherence, instruction fusion, and support for the RISC-V Advanced Interrupt Architecture 1.0.

StarFive claims performance of 15 SPECint2006 per GHz and 10.0 Dhrystone v2.2 per MHz.

Those are vendor-provided figures, so real silicon and independent testing will be needed before making direct performance comparisons, but they make the class of processor StarFive is targeting clear.

Vector processing is another major part of the design.

The core supports integer operations across 8-, 16-, 32-, and 64-bit data, along with FP16, FP32, FP64, and BF16 floating point, using a 256-bit vector length. StarFive's vector processing unit includes two vector pipelines and two floating-point pipelines.

This isn't just a paper architecture, either.

StarFive says Dubhe-100 has already been adopted by customers and has entered the development stage for server CPU chips.

One of those customers is LECARC, which announced in June that it would use StarFive's Dubhe-100 IP, under the product name Fang·TianShu-100, to co-develop next-generation server processors for intelligent edge computing.

That's important because RISC-V's biggest challenge is no longer proving that the architecture can boot Linux.

We've had RISC-V Linux boards for years.

The next challenge is proving that RISC-V can scale into the same markets currently dominated by high-performance Arm and x86 processors, including servers, cloud infrastructure, AI inference, storage systems, and other workloads where single-thread performance, memory bandwidth, virtualization, cache coherence, and mature software support all matter.

Dubhe-100 is clearly designed with that world in mind.

Its support for RVA23 is also increasingly important as high-performance RISC-V hardware becomes more standardized.

Early RISC-V boards often varied considerably in which optional ISA extensions they implemented. Profiles like RVA23 establish a more predictable baseline for application processors, giving operating systems and software developers a clearer idea of which features they can expect to be present.

On the software side, StarFive is offering Dubhe-100 through its StarStudio IDE with two SDK options: a bare-metal SDK built around GCC/LLVM, GDB, and OpenOCD, and a Linux SDK bundling Yocto, Linux Kernel 6.18, OpenSBI, and U-Boot.

For makers, you're probably not going to buy a Dubhe-100 development board next month.

But that's not really why this matters.

Companies like StarFive built much of their reputation through inexpensive RISC-V development hardware. Seeing that same ecosystem move toward genuine server-class CPU designs is another sign that RISC-V is growing beyond its embedded and experimental roots.

That brings us neatly to Linux 7.2, which officially became the latest mainline Linux kernel on August 16.

Linux 7.2 is a large update covering everything from CPU scheduling and graphics to storage, networking, and hardware drivers.

For SSBytes readers, though, some of the most interesting changes are around RISC-V and Arm SBC support.

One particularly timely change is that the default maximum number of CPUs supported by a standard 64-bit RISC-V kernel configuration has been increased from 64 to 256.

Most maker boards obviously aren't about to need 256 CPU cores, but the change says something about where the architecture is heading.

Kernel developers pointed to SpacemiT's 80-core RVA23 RISC-V server and the earlier dual-socket, SG2042-based Sophgo Pisces system with 128 cores as evidence that a 64-core ceiling was no longer enough.

Linux's default RISC-V configuration was originally built around much smaller systems. Raising that ceiling makes more sense now that companies such as StarFive are talking seriously about many-core server processors.

Linux 7.2 also enables ESWIN SoC support in the default RISC-V kernel configuration, benefiting hardware such as SiFive's HiFive Premier P550 development board.

Support for UltraRISC hardware is also enabled in the default configuration for the first time, covering the octa-core UR-DP1000 and its UR-CP100 cores, the chip behind systems such as the Milk-V Titan mini-ITX board.

There are several less visible improvements as well.

RISC-V now uses build-time sorting for the kernel's __mcount_loc section, reducing some startup overhead during ftrace initialization. Linux 7.2 also includes a collection of memory-management, cache-info, stack-walking, and misaligned-access fixes for the architecture.

Arm boards get plenty of attention too.

For Rockchip hardware, Linux 7.2 adds basic camera support for the RK3588, including the VICAP capture interface, along with additional peripheral enablement.

RK3528 gains USB PHY support and more device-tree work, while RK3588 receives additional I2S clock support and other updates.

Allwinner hardware also gets several improvements, including MIPI CSI-2 support for the A83T, timer improvements for D1s/T113 and H616 systems, and device-tree overlay support for PINE64 boards.

Beyond SBCs, Linux 7.2 introduces cache-aware scheduling, designed to keep tasks that share data closer together within the same last-level cache domain.

The release also adds USB4STREAM for high-speed system-to-system transfers over USB4 and Thunderbolt, along with a large collection of AMD and Intel hardware improvements and initial Apple M3 support.

None of these features individually transform Linux.

That's usually not how kernel support works.

What matters for SBCs is the steady accumulation of upstream support.

A board that permanently relies on a manufacturer-modified Linux 5.x kernel may work perfectly when it's new, but it becomes increasingly difficult to maintain as the rest of the Linux ecosystem moves forward.

Mainline support gives hardware a much better chance of continuing to work years after the manufacturer has moved on.

That's especially important in the RISC-V world, where new processors, ISA extensions, and SoCs are appearing quickly.

These three stories show two very different sides of the Linux hardware ecosystem.

PINE64 is dealing with the economics of building inexpensive physical hardware. Even with open designs and open-source software, you still need affordable DRAM, flash, and other components to turn those designs into something people can actually buy.

StarFive is tackling the opposite problem: proving that RISC-V can move beyond inexpensive development boards and scale into high-performance server processors.

Linux 7.2 sits underneath both worlds, steadily expanding support for larger RISC-V systems while continuing to improve the Arm and RISC-V boards makers are using today.

That contrast may be the most interesting part.

The low end of Linux computing is being squeezed by component costs at the same time that RISC-V is becoming ambitious enough to target servers with hundreds of CPU cores.

Open hardware isn't moving in just one direction anymore.

It's spreading outward, from tiny embedded systems and affordable SBCs all the way to server-class processors, and the challenges at each end are becoming very different.